1. Field of the Invention
The present invention relates to a basic cell realized in the (complementary-metal-oxide-semiconductor) (CMOS) technique for building up electrical circuits, whereby a plurality of transistors are arranged next to one another, whereby first interconnects essentially composed of polysilicon are arranged parallel to the extent of the transistors, second interconnects essentially composed of metal are arranged perpendicular to the first interconnects, and the second interconnects extend either above the transistors or between the transistors, and to a method for the automatic generation of such a basic cell in accordance with the German patent application No. P 34 22 715.6, fully incorporated herein by this reference.
2. Description of the Prior Art
The increasing complexity of very large scale integrated (VLSI) electrical circuits requires an increasingly more difficult manual design of the circuit layout. The great number of discrete geometrical structures forces a switch to automatic layout generation. In such a layout generation method, the geometrical layout structures are acquired from an abstract circuit description with the assistance of software. The individual layout rectangles are thereby dimensioned and placed by means of a program. The particular advantages of a layout generation via software are high flexibility, fast adaptation to new design rules and short design times.
The overall layout of anelectrical circuit is formed from a plurality of such layout rectangles. In the personal design of the electronic circuit, each rectangle is individually dimensioned and individually located. Given such a method, however, the complexity is not reduced, so that the layout of larger circuits can only be generated with a high expense. The gate-matrix method, by contrast, reduces the complexity of the circuit design since only defined grid points of a matrix are permitted for the placement of the geometrical structures. In accordance with the gate-matrix principle, layouts are generated in the scope of standard cells and are subsequently further processed with traditional methods. Another method for automatic layout generation of even involved VLSI circuits reduces the complexity of the circuit design with the assistance of the basic cell concept. A layout is thereby constructed of highly-paramaterized basic cells. The relative arrangement of individual geometrical structures relative to one another is roughly prescribed within a basic cell. Further methods for the production of the electronic circuits can be derived, for example, from the brochure CAD fur VLSI by H. G. Schwartzel, Springer-Verlag, 1982, for example on Pages 63-76, fully incorporated herein by this reference.